In the design of a semiconductor device using a computer (CAD system), a layout design is performed based on a netlist (information indicating a connection relationship of logic elements), after logic design of designing a logic circuit of a gate level is performed. When the layout is determined, various verifications are performed regarding whether the layout satisfies a design rule and whether a device having the layout normally operates. As one of processes performed in the verification process, LPE (Layout Parameter Extraction) has been known (see Japanese Patent Application Laid-open No. 2006-209702).
In the LPE, parasitic resistance and parasitic capacitance (hereinafter, “parasitic parameters”) concerning wiring in the obtained layout are extracted. The parasitic parameters can be determined for the first time after the layout is obtained, and are not contained in the above netlist. The extracted parasitic parameters are added to the above netlist, and, as a result, the netlist added with the parasitic parameters (hereinafter, a “netlist having parasitic parameters”) is generated. In other words, the netlist having parasitic parameters can be obtained, by inputting the netlist and the layout data to a tool that executes the LPE (LPE tool).
Thereafter, delay verification and timing verification of the device which is being designed are performed using the obtained netlist having parasitic parameters. When results of these verifications are “fail”, the layout design process is executed again. The LPE processing is then executed again, and verifications are executed again. The above operation is repeated until when the layout “passes” the verifications. When the results of the verifications “pass”, final layout data is determined.
There are also other various techniques concerning the layout design. For example, Japanese Patent Application Laid-open No. H11-265941 discloses a method of decreasing design cost by shortening the LSI design time, in designing the LSI having circuits of mutually different signal amplitudes mounted in the same chip. In this method, LEF information is data-converted from an actual wiring layer or a terminal layer of the chip and each function block to a virtual wiring layer of an independent definition. Wiring is performed automatically in the virtual wiring layer based on the converted information and circuit connection information. This automatic wiring information is data-converted to the actual wiring layer or the terminal layer, thereby decreasing the number of times of the automatic wiring.
In a semiconductor device, a miniaturized product of an existing product is often designed. In this case, the layout of a part requiring a correction is designed in concentration, while following the layout of the existing product. Therefore, efficient layout design can be performed.
However, the LPE processing of the layout of the miniaturized product cannot be performed until after the layout data of the miniaturized product is created anew. As described above, the LPE is the processing of extracting parasitic parameters, and the parasitic parameters can be determined only after obtaining the layout. Therefore, even when a miniaturized product is attempted to be designed based on the layout of the existing product, parasitic capacitance and parasitic resistance for performing the delay verification and the timing verification cannot be extracted, until after the layout data is designed. In other words, according to the conventional design method, the parasitic parameters already obtained in the layout of the existing product cannot be used, and it takes time from the layout designing to the passing of the verifications due to the increase in the number of repetition of designing. As a result, the designing is inefficient.